The present disclosure relates to digital phase-locked loop (PLL) circuits outputting a clock signal with a frequency of a given magnification ratio, which is synchronized with a reference signal, and communication devices using the PLL circuits.
A conventional general digital PLL circuit includes, as shown in FIG. 20, a reference phase accumulator (RPA) 201 operating with a reference signal FREF, a variable phase accumulator (VPA) 202 operating with an output clock CKV, a phase comparator 203, a loop filter 204, and an oscillator 206.
The digital PLL circuit operates so that the frequency of the output clock CKV is frequency command word (FCW) times as large as the frequency of the reference signal FREF. For example, when an output clock of 225 MHz is to be obtained where the frequency of the reference signal FREF is 100 MHz, the frequency command word FCW may be set to 2.25. The RPA 201 is synchronized with the reference signal FREF, and integrates the frequency command word FCW to calculate a reference phase value RHR. On the other hand, the VPA 202 is synchronized with the output clock CKV and increments one to calculate a variable phase value PHV of the output clock CKV. The frequency command word FCW corresponds to the frequency of the output clock CKV normalized by the frequency of the reference signal FREF. Thus, where a phase update value of one pulse width of the reference signal FREF is the frequency command word FCW, one pulse of the output clock CKV is regarded as one phase update value. Therefore, the phase value PHR of the reference signal FREF and the phase value PHV of the output clock CKV can be compared at the same level. The phase comparator 203 obtains a difference between the phase value PHR of the reference signal FREF and the phase value PHV of the output clock CKV to calculate a phase error. The phase error is smoothed by the loop filter 204. An oscillation frequency of the oscillator 206 is controlled to a desired value by an output of the loop filter 204.
Where the value of the frequency command word FCW is an integer, the pulse number of the output clock CKV included in one pulse of the reference signal FREF is always a constant value (a frequency command word FCW), and is thus easily synchronized.
However, when the frequency command word FCW contains a fractional component, the pulse number of the output clock CKV included in one pulse of the reference signal FREF is not always constant. FIG. 21 is an operation timing chart of the PLL circuit shown in FIG. 20, where the frequency command word FCW is 2.25. As can be seen from FIG. 21, since the frequency ratio of the reference signal FREF to the output clock CKV is not always an integer, even if phase comparison is carried out to synchronize with the output clock CKV or the reference signal FREF, a minute residual phase error is always mixed in calculation of a phase error to degrade phase noise characteristics.
In order to solve the problem, Japanese Patent Publication No. 2002-76886 employs the configuration of a PLL circuit shown in FIG. 22. The block to be focused is a time-to-digital converter (TDC) 312 calculating a minute residual phase error. FIG. 23 illustrates the configuration of the TDC. The TDC 312 includes a delay line of the inverter chain 3121, a register group 3122 storing outputs of the delay line 3121 by edges of the reference signal FREF, an edge detector 3123 detecting time between edges of the reference signal FREF and the output clock CKV, and an output section 3124 calculating a minute phase error based on the result of the edge detection. Note that, in FIG. 22, 301 denotes an RPA, 302 denotes a VPA, 303 denotes a phase comparator, 304 denotes a loop filter, 305 denotes a control amount generator, 306 denotes an oscillator, 309 denotes a register circuit synchronized with the output clock CKV and generating a signal CKR, which obtained by retiming the reference signal FREF, and 310 denotes a register circuit operating in synchronization with the retiming signal CKR.
A calculation method of the minute phase error will be described below. The output clock CKV is input to the delay line 3121. That is, outputs of the inverters are delayed signals of the output clock CKV. Since the delay line 3121 is actually an inverter chain, the inverters at even number stages have the same polarity, and the inverters at odd number stages have the inverted polarity. Note that, as shown in FIG. 23, the polarity can be uniform by maintaining the integrity with outputs of the register group receiving the outputs of the inverters. As such, the polarity of the output clock CKV at the edges of the reference signal FREF is stored in the register group. In both cases where a phase error has a positive value as shown in FIG. 24A and where the phase error has a negative value as shown in FIG. 24C, data portions D[0], D[1], D[2], . . . , which are gradually delayed by minute time, can be obtained from the register group 3122 as shown in FIG. 24B by the delay line 3121 and the register group 3122 shown in FIG. 24B. With use of the information, time Δtr between rising edges of the reference signal FREF and the output clock CKV, and time Δtf between falling edges of the reference signal FREF and the output clock CKV can be represented by digital values. An output section 3124 can calculate the minute phase error as shown in equations (1) using the time Δtr between the rising edges and the time Δtf between the falling edges.Tν=2×|Δtf−Δtr|ε=Tν−Δtr  Equations (1)(Where Tν is a Period of the Output Clock CKV1, and ε is the Minute Phase Error.)
Note that, the pulse interval of the output clock CKV needs to be normalized as one for calculation, a sufficient number of taps needs to be secured in the delay line for covering one pulse of the output clock CKV.
As such, in the configuration shown in Japanese Patent Publication No. 2002-76886, the TDC 312 extracts a minute phase error between the reference signal FREF and the output clock CKV to reflect in the PLL circuit, thereby obtaining a significant improvement in phase noise characteristics.
However, the area of the TDC 312 is structurally difficult to reduce, since an inverter chain with a sufficient length is needed to cover one period of the output clock CKV to detect the rising/falling edges of the reference signal FREF and the output clock CKV. Also, when a frequency magnification ratio FCW to the reference signal FREF becomes large, the speed of the clock signal CKV input to the inverter chain 3121 increases, thereby increasing power consumption. Furthermore, since outputs of the inverters need to be provided at regular time intervals, connections between the inverters need to equal lengths to increase the design difficulty.